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CY7C373i
UltraLogicTM 64-Macrocell Flash CPLD
Features
* 64 macrocells in four logic blocks * 64 I/O pins * 5 dedicated inputs including 4 clock pins * In-System ReprogrammableTM (ISRTM) Flash technology -- JTAG interface * Bus Hold capabilities on all I/Os and dedicated inputs * No hidden delays * High speed -- fMAX = 125 MHz -- tPD = 10 ns -- tS = 5.5 ns -- tCO = 6.5 ns * Fully PCI compliant * 3.3V or 5.0V I/O operation * Available in 84-pin PLCC and 100-pin TQFP packages * Pin compatible with the CY7C374i
Functional Description
The CY7C373i is an In-System Reprogrammable Complex Programmable Logic Device (CPLD) and is part of the FLASH370iTM family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C373i is designed to bring the ease of use and high performance of the 22V10, as well as PCI Local Bus Specification support, to high-density CPLDs. Like all of the UltraLogicTM FLASH370i devices, the CY7C373i is electrically erasable and In-System Reprogrammable (ISR), which simplifies both design and manufacturing flows, thereby reducing costs. The Cypress ISR function is implemented through a JTAG serial interface. Data is shifted in and out through the SDI and SDO pins.The ISR interface is enabled using the programming voltage pin (ISREN). Additionally, because of the superior routability of the FLASH370i devices, ISR often allows users to change existing logic designs while simultaneously fixing pinout assignments.
CLOCK INPUTS
Logic Block Diagram
INPUT
1 INPUT MACROCELL 2 16 I/Os I/O0-I/O15 LOGIC BLOCK A
4 INPUT/CLOCK MACROCELLS 2 16 I/Os I/O48-I/O63
36 16
PIM
36 16
LOGIC BLOCK D
16 I/Os I/O16-I/O31
LOGIC BLOCK B
36 16
36 16
LOGIC BLOCK C
16 I/Os I/O32-I/O47
32
32
Selection Guide
7C373i-125 7C373i-100 Maximum Propagation Delay[1], tPD (ns) Minimum Set-up, tS (ns) Maximum Clock to Output[1], tCO (ns) Typical Supply Current, ICC (mA) 10 5.5 6.5 75 12 6.0 6.5 75 7C373i-83 15 8 8 75 7C373iL-83 15 8 8 45 7C373i-66 20 10 10 75 7C373iL-66 20 10 10 45
Note: 1. The 3.3V I/O mode timing adder, t3.3IO, must be added to this specification when VCCIO = 3.3V.
Cypress Semiconductor Corporation Document #: 38-03030 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised April 8, 2004
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Pin Configurations
PLCC Top View
I/O 2 I/O 1 I/O 0 VCCINT GND VCCIO ISREN I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 GND I/O 7 I/O 6 I/O 5 I/O 4 I/O 3
CY7C373i
11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 I/O8 I/O9 I/O10/SCLK I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I 0 VCCIO GND CLK1/I 1 I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 GND 74 12 73 13 72 14 71 15 70 16 69 17 68 18 67 19 66 20 65 21 64 7C373 22 63 23 62 24 61 25 60 26 59 27 58 28 57 29 56 30 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 I/O26 /SMODE I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCCINT GND VCCIO I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38/SDO I/O39 GND I/O24 I/O25 GND I/O55 I/O54 /SDI I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I 4 GND VCCIO CLK2/I 3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40
TQFP Top View
I/O 0 VCCINT NC VCCIO I/O 7 I/O 6 I/O 5 VCCIO NC GND ISREN I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 GND NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O 4 I/O 3 I/O 2 I/O 1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 SCLK GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 CLK0/I0 VCCIO N/C GND CLK1/I1 I/O15 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCCIO NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDI VCCIO I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 CLK3/I4 GND NC VCCIO CLK2/I3 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 GND NC
SMODE
I/O35 I/O36 I/O37 I/O38 I/O39 VCCIO
GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29
VCCINT
I/O30 I/O31 I2
Document #: 38-03030 Rev. *A
NC GND VCCIO I/O32 I/O33 I/O34
SDO
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Functional Description
The 64 macrocells in the CY7C373i are divided between four logic blocks. Each logic block includes 16 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370i architecture are connected with an extremely fast and predictable routing resource--the Programmable Interconnect Matrix (PIM). The PIM brings flexibility, routability, speed, and a uniform delay to the interconnect. Like all members of the FLASH370i family, the CY7C373i is rich in I/O resources. Every macrocell in the device features an associated I/O pin, resulting in 64 I/O pins on the CY7C373i. In addition, there is one dedicated input and four input/clock pins. Finally, the CY7C373i features a very simple timing model. Unlike other high-density CPLD architectures, there are no hidden speed delays such as fanout effects, interconnect delays, or expander delays. Regardless of the number of resources used or the type of application, the timing parameters on the CY7C373i remain the same. Logic Block The number of logic blocks distinguishes the members of the FLASH370i family. The CY7C373i includes four logic blocks. Each logic block is constructed of a product term array, a product term allocator, and 16 macrocells. Product Term Array The product term array in the FLASH370i logic block includes 36 inputs from the PIM and outputs 86 product terms to the product term allocator. The 36 inputs from the PIM are available in both positive and negative polarity, making the overall array size 72 x 86. This large array in each logic block allows for very complex functions to be implemented in single passes through the device. Product Term Allocator The product term allocator is a dynamic, configurable resource that shifts product term resources to macrocells that require them. Any number of product terms between 0 and 16 inclusive can be assigned to any of the logic block macrocells (this is called product term steering). Furthermore, product terms can be shared among multiple macrocells. This means that product terms that are common to more than one output can be implemented in a single product term. Product term steering and product term sharing help to increase the effective density of the FLASH370i CPLDs. Note that the product term allocator is handled by software and is invisible to the user. I/O Macrocell Each of the macrocells on the CY7C373i has a separate I/O pin associated with it. In other words, each I/O pin is shared by two macrocells. The input to the macrocell is the sum of between 0 and 16 product terms from the product term allocator. The macrocell includes a register that can be optionally bypassed, polarity control over the input sum-term, and two global clocks to trigger the register. The macrocell also features a separate feedback path to the PIM so that the register can be buried if the I/O pin is used as an input. Programmable Interconnect Matrix
CY7C373i
The Programmable Interconnect Matrix (PIM) connects the four logic blocks on the CY7C373i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM. Programming For an overview of ISR programming, refer to the FLASH370i Family data sheet and for ISR cable and software specifications, refer to ISR data sheets. For a detailed description of ISR capabilities, refer to the Cypress application note, "An Introduction to In System Reprogramming with FLASH370i." PCI Compliance The FLASH370i family of CMOS CPLDs are fully compliant with the PCI Local Bus Specification published by the PCI Special Interest Group. The simple and predictable timing model of FLASH370i ensures compliance with the PCI AC specifications independent of the design. On the other hand, in CPLD and FPGA architectures without simple and predictable timing, PCI compliance is dependent upon routing and product term distribution. 3.3V or 5.0V I/O operation The FLASH370i family can be configured to operate in both 3.3V and 5.0V systems. All devices have two sets of VCC pins: one set, VCCINT, for internal operation and input buffers, and another set, VCCIO, for I/O output drivers. VCCINT pins must always be connected to a 5.0V power supply. However, the VCCIO pins may be connected to either a 3.3V or 5.0V power supply, depending on the output requirements. When VCCIO pins are connected to a 5.0V source, the I/O voltage levels are compatible with 5.0V systems. When VCCIO pins are connected to a 3.3V source, the input voltage levels are compatible with both 5.0V and 3.3V systems, while the output voltage levels are compatible with 3.3V systems. There will be an additional timing delay on all output buffers when operating in 3.3V I/O mode. The added flexibility of 3.3V I/O capability is available in commercial and industrial temperature ranges. Bus Hold Capabilities on all I/Os and Dedicated Inputs In addition to ISR capability, a new feature called bus-hold has been added to all FLASH370i I/Os and dedicated input pins. Bus-hold, which is an improved version of the popular internal pull-up resistor, is a weak latch connected to the pin that does not degrade the device's performance. As a latch, bus-hold recalls the last state of a pin when it is three-stated, thus reducing system noise in bus-interface applications. Bus-hold additionally allows unused device pins to remain unconnected on the board, which is particularly useful during prototyping as designers can route new signals to the device without cutting trace connections to VCC or GND. Design Tools Development software for the CY7C371i is available from Cypress's WarpTM, Warp ProfessionalTM, and Warp EnterpriseTM software packages. Please refer to the data sheets on these products for more details. Cypress also actively supports almost all third-party design tools. Please refer to third-party tool support for further information.
Document #: 38-03030 Rev. *A
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................-65C to +150C Ambient Temperature with Power Applied...............................................-55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ............................................... -0.5V to +7.0V DC Input Voltage............................................ -0.5V to +7.0V DC Program Voltage .....................................................12.5V Output Current into Outputs.........................................16 mA Industrial -40C to +85C
CY7C373i
Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Range Commercial Ambient Temperature 0C to +70C VCC VCCINT 5V 0.25V VCCIO 5V 0.25V OR 3.3V 0.3V 5V 0.5V OR 3.3V 0.3V
5V 0.5V
Electrical Characteristics Over the Operating Range[2]
Parameter VOH VOHZ VOL VIH VIL IIX IOZ IOS ICC IBHL IBHH IBHLO IBHHO Description Output HIGH Voltage Output HIGH Voltage with Output Disabled[7] Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current VCC = Min. VCC = Max. VCC = Min. IOH Test Conditions = -3.2 mA (Com'l/Ind)[3] (Com'l/Ind)[3, 4] (Com'l/Ind)[3, 4] Inputs[5] Inputs[5] IOH = 0 A IOL Min. 2.4 4.0 3.6 0.5 2.0 -0.5 -10 -50 0 -30 Com'l/Ind. Com'l "L", -66 +75 -75 +500 -500 75 45 -70 Disabled[4] 7.0 0.8 +10 +50 -125 -160 125 75 Typ. Max. Unit V V V V V V A A A mA mA mA A A A A
IOH = -50 A
= 16 mA (Com'l/Ind)[3]
Guaranteed Input Logical HIGH Voltage for all Guaranteed Input Logical LOW Voltage for all VI = Internal GND, VI = VCC VCC = Max., VO = 3.3V, Output
Output Leakage Current VCC = Max., VO = GND or VO = VCC, Output Disabled Output Short Circuit Current[6, 7] VCC = Max., VOUT = 0.5V
Power Supply Current[8] VCC = Max., IOUT = 0 mA, f = 1 MHz, VIN = GND, VCC Input Bus Hold LOW Sustaining Current Input Bus Hold HIGH Sustaining Current Input Bus Hold LOW Overdrive Current Input Bus Hold HIGH Overdrive Current VCC = Min., VIL = 0.8V VCC = Min., VIH = 2.0V VCC = Max. VCC = Max.
Notes: 2. If VCCIO is not specified, the device can be operating in either 3.3V or 5V I/O mode; VCC=VCCINT. 3. IOH = -2 mA, IOL = 2 mA for SDO. 4. When the I/O is three-stated, the bus-hold circuit can weakly pull the I/O to a maximum of 4.0V if no leakage current is allowed. This voltage is lowered significantly by a small leakage current. Note that all I/Os are three-stated during ISR programming. Refer to the application note "Understanding Bus Hold" for additional information. 5. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included. 6. Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.
Document #: 38-03030 Rev. *A
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Capacitance[7]
Parameter CIN[9] CCLK Description Input Capacitance Clock Signal Capacitance Test Conditions VIN = 5.0V at f = 1 MHz VIN = 5.0V at f = 1 MHz 5 Min. Max. 8 12
CY7C373i
Unit pF pF
Inductance[7]
Parameter L Description Maximum Pin Inductance Test Conditions VIN = 5.0V at f = 1 MHz 100-Pin TQFP 8 84-Lead PLCC 8 Unit nH
Endurance Characteristics[7]
Parameter N Description Maximum Reprogramming Cycles Test Conditions Normal Programming Conditions Max. 100 Unit Cycles
AC Test Loads and Waveforms
238 (COM'L) 5V OUTPUT 35 pF INCLUDING JIG AND SCOPE 5V OUTPUT 170 (COM'L) 5 pF 236 (MIL) INCLUDING JIG AND SCOPE 238 (COM'L) 319 (MIL) 3.0V 90% GND < 2 ns 170 (COM'L) 10% 90% 10% < 2 ns ALL INPUT PULSES
(a)
Equivalent to: THE VENIN EQUIVALENT 99 (COM'L) 2.08V(COM'L)
(b)
(c)
OUTPUT
Parameter[10] tER(-)
Vx 1.5V V OH
Output Waveform-Measurement Level
0.5V
VX
tER(+)
2.6V V OL 0.5V VX
tEA(+)
1.5V 0.5V VX V OH
tEA(-)
Vthe VX 0.5V V OL
(d) Test Waveforms
Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. Measured with 16-bit counter programmed into each logic block. 9. CI/O for dedicated Inputs, and I/Os with JTAG functionality is 12 pF Max., and for ISREN is 15 pF Max. 10. tER measured with 5-pF AC Test Load and tEA measured with 35-pF AC Test Load.
Document #: 38-03030 Rev. *A
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Switching Characteristics Over the Operating Range[11]
7C373i-125 Parameter tPD tPDL tPDLL tEA tER tWL tWH tIS tIH tICO tICOL Description Input to Combinatorial Output[1] Input to Output Through Transparent Input or Output Latch[1] Input to Output Through Transparent Input and Output Latches[1] Input to Output Enable[1] Input to Output Disable Clock or Latch Enable Input LOW Time[7] Clock or Latch Enable Input HIGH Time[7] Input Register or Latch Set-Up Time Input Register or Latch Hold Time Input Register Clock or Latch Enable to Combinatorial Output[1] Input Register Clock or Latch Enable to Output Through Transparent Output Latch[1] Clock or Latch Enable to Output[1] Set-Up Time from Input to Clock or Latch Enable Register or Latch Data Hold Time Output Clock or Latch Enable to Output Delay (Through Memory Array)[1] Output Clock or Latch Enable to Output Clock or Latch Enable (Through Memory Array) Set-Up Time from Input Through Transparent Latch to Output Register Clock or Latch Enable Hold Time for Input Through Transparent Latch from Output Register Clock or Latch Enable Maximum Frequency with Internal Feedback (Least of 1/tSCS, 1/(tS + tH), or 1/tCO)[7] Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH), 1/(tS + tH), or 1/tCO)[7] Maximum Frequency of (2) CY7C373is with External Feedback (Lesser of 1/(tCO + tS) and 1/(tWL + tWH)[7] Output Data Stable from Output clock Minus Input Register Hold Time for 7C37x[7, 12] 8 10 5.5 0 14 10 12 3 3 2 2 14 16 Min. Max. 10 13 15 14 14 3 3 2 2 16 18 Combinatorial Mode Parameters 12 15 16 16 16 4 4 3 3 19 21 15 18 19 19 19 7C373i-100 Min. Max. 7C373i-83 7C373iL-83 Min. Max.
CY7C373i
7C373i-66 7C373iL-66 Min. Max. 20 22 24 24 24 5 5 4 4 24 26 Unit ns ns ns ns ns ns ns ns ns ns ns
Input Registered/Latched Mode Parameters
Output Registered/Latched Mode Parameters tCO tS tH tCO2 tSCS tSL 6.5 6 0 16 12 15 6.5 8 0 19 15 20 8 10 0 24 10 ns ns ns ns ns ns
tHL fMAX1 fMAX2
0 125 153.8
0 100 153.8
0 83 125
0 66 100
ns MHz MHz
fMAX3
83.3
80
62.5
50
MHz
tOH-tIH 37x
0
0
0
0
ns
Notes: 11. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 12. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C373i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03030 Rev. *A
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Switching Characteristics Over the Operating Range[11] (continued)
7C373i-125 Parameter tICS fMAX4 Description Input Register Clock to Output Register Clock Maximum Frequency in Pipelined Mode (Least of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or 1/tSCS)[7] Asynchronous Reset Width[7] Asynchronous Reset Recovery Time Asynchronous Reset to Output[1] Asynchronous Preset Width[7] Time[7] Output[1] 500 1 10 12 16 500 1 Asynchronous Preset Recovery Asynchronous Preset to
[7]
CY7C373i
7C373i-83 7C373iL-83 Min. 12 66.6 Max. 7C373i-66 7C373iL-66 Min. 15 50.0 Max. Unit ns MHz
7C373i-100 Min. 10 83.3 Max.
Min. 8 125
Max.
Pipelined Mode Parameters
Reset/Preset Parameters tRW tRR tRO tPW tPR tPO fTAP t3.3IO 10 12 16 12 14 18 500 1 12 14 18 15 17 21 500 1 15 17 21 20 22 26 20 22 26 ns ns ns ns ns ns kHz ns
Tap Controller Parameter Tap Controller Frequency 3.3V I/O mode timing adder 3.3V I/O Mode Parameters
Switching Waveforms
Combinatorial Output
INPUT tPD COMBINATORIAL OUTPUT
Registered Output
INPUT tS CLOCK tCO REGISTERED OUTPUT tWH tWL tH
CLOCK
Document #: 38-03030 Rev. *A
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Switching Waveforms (continued)
Latched Output
INPUT tS LATCH ENABLE tPDL LATCHED OUTPUT tCO tH
CY7C373i
Clock to Clock
REGISTERED INPUT
INPUT REGISTER CLOCK tICS OUTPUT REGISTER CLOCK tSCS
Latched Input
LATCHED INPUT tIS LATCH ENABLE tPDL COMBINATORIAL OUTPUT tICO tIH
tWH LATCH ENABLE
tWL
Document #: 38-03030 Rev. *A
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Switching Waveforms (continued)
Latched Input and Output
LATCHED INPUT
CY7C373i
tPDLL LATCHED OUTPUT tICOL INPUT LATCH ENABLE tICS OUTPUT LATCH ENABLE tSL tHL
tWH LATCH ENABLE
tWL
Asynchronous Reset
tRW INPUT tRO REGISTERED OUTPUT tRR CLOCK
Asynchronous Preset
tPW INPUT tPO REGISTERED OUTPUT tPR CLOCK
Document #: 38-03030 Rev. *A
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Switching Waveforms (continued)
Output Enable/Disable
INPUT tER OUTPUTS tEA
CY7C373i
Ordering Information
Speed (MHz) 125 100 Ordering Code CY7C373i-125AC CY7C373i-125JC CY7C373i-100AC CY7C373i-100JC CY7C373i-100AI CY7C373i-100JI 83 CY7C373i-83AC CY7C373i-83JC CY7C373i-83AI CY7C373i-83JI CY7C373iL-83JC 66 CY7C373i-66AC CY7C373i-66JC CY7C373i-66AI CY7C373i-66JI CY7C373iL-66JC Package Type A100 J83 A100 J83 A100 J83 A100 J83 A100 J83 J83 A100 J83 A100 J83 J83 Package Type 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 100-Pin Thin Quad Flatpack 84-Lead Plastic Leaded Chip Carrier 84-Lead Plastic Leaded Chip Carrier Commercial Industrial Commercial Commercial Industrial Commercial Industrial Commercial Operating Range Commercial
Document #: 38-03030 Rev. *A
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Package Diagrams
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
CY7C373i
51-85048-*B
84-Lead Plastic Leaded Chip Carrier J83
51-85006-*A
Warp is a registered trademark and Ultra37000, FLASH370, FLASH370i, ISR, UltraLogic, Warp Professional, and Warp Enterprise are trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-03030 Rev. *A Page 11 of 12
(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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Document History Page
Document Title: CY7C373i UltraLogicTM 64-Macrocell Flash CPLD Document Number: 38-03030 REV. ** *A ECN NO. Issue Date 106375 213375 09/17/01 See ECN Orig. of Change SZV FSG Description of Change Change from Spec number: 38-00495 to 38-03030
CY7C373i
Added note to title page: "Use Ultra37000 For All New Designs"
Document #: 38-03030 Rev. *A
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